Reference :
http://www.slideshare.net/itembedded/verilog-14596615
命名大小寫有差別,
reg add與reg
Add不一樣
所有的關鍵字都是小寫
如module, endmodule
不可以以數字為命名的起始,如23a,
a24可以
用來描述位元的字母大小寫不分,如4'd10與4'D10
相同
如果將負數assigned至一個integer
numbers時,則會以2次補數填入
wire還有其他的姊妹,如wor(wired
ourput 'OR' together),wand(wired ourput 'AND' together)
除法運算子(/)與取餘數運算子(%)沒有辦法合成
若reg的值有任一為'x'的話,則結果會是'x'
如
4'b00x1 + 4b'001x = 4'b00xx
a === b
判斷包括'z'或'x'
a !== b
判斷包括'z'或'x'
a == b
判斷不包括'z'或'x'
a != b
判斷不包括'z'或'x'
{n{m}} =>
replicate value m, n times
{b,{3{c,d}}} =>
{b,c,d,c,d,c,d}
<cond_expr> ?
<true_expr> : <false_expr>;
y= en1 ? dout1 : en2 ?
dout2 : 1'b0
當en1為1時,
y等於dout1,若en1為0
且en2為1,則y等於
dout2,否則y為0
initial只會執行一次,用在simulation,always則會始終循環執行.其內指定的Data
type都要是reg
sequential =>
begin – end
sequential =>
fork – join
blocking => '=',
用在combinational
logic
在同一個程序裡,執行順序按照code的順序
non-blocking =>
'<=' , 用在sequential
logic
在同一個程序裡,所有的code同時執行
casez
: 'z' as dont care
casex
: 'z' and 'x' as dont care
#<time><執行式>;
#15 reset = '1'
always@(posedge clk or
negedge rst)
begin
if(rst
== 1'b0)
begin
a <= 1'b0;
end
else
begin
a <= b;
end
end
task可以有任意數量的輸入,但只能有一個輸出,可以被調用多次,減少代碼重複
不能使用posedge,negedge,#delay
task內可以再次呼叫task,或是呼叫function
但是function
內不能呼叫task
function可以有多個輸出
$display,$strobe,$monitor
皆用在simulation時顯示文字
$display,$strobe =>
每次執行時顯示一次
$monitor =>
用於參數有改變時就顯示一次
%d(decimal),%c(character),%t(time),%m(hierarchy
level)
$display(„show
string“,a,b)
$displayb(as
above but defaults to binary),displayh,displayo
…. monitor,strobe 以此類推
$time,$stime,$realtime
return the current
simulation time as 64 bit integer,32 bit integer, real number
$reset
=> reset the simulation back to time 0
$stop
=> stop simulator and into command mode
$finish =>
exit the simulator
$scope(hierarchy_name)
=> set the current hierarchical scope to hierarchy_name
$showscopes(n)
=> lists all modules,tasks and block names in the current scope
$random
=> generates a random integer every time it is called.
Only for debussy
$dumpfile(„filename.vcd“)
$dumpvar(n,top)
dumps all the variables in module top and n-1 levels below
$dumpon initiates
the dump
$dumpoff
stop dumping
$dumpall
$fopen
$fdisply
$fstrobe
$fmonitor
$fwrite
defparam
用來重新設定預設的參數,此過程叫做parameter
overriding