Virtex6 DDR3 Setting

Referece: Virtex-6 FPGA Memory Interface Solutions User Guide UG406

之前都用ML605,所以板子相關設定都已經用好了

最近需要移植到比較小的virtex6,我先使用的型號是xc6vcx75t,

再這上面在DDR3上面有一些小細節要注意一下

建立microblaze以後會出現這樣一個訊息

表示DDR3的IP還需要經過一些設定

打開DDR3 IP 建立新的設定

DDR3中的一些東西還沒研究要怎麼設定,所以都先照預設值

建立好以後按design rule check出現下列錯誤訊息

ERROR:EDK:4070 - INSTANCE: clock_generator_0, PORT: PSCLK - invalid port in use when ISVALID="(C_CLKOUT15_VARIABLE_PHASE || C_CLKOUT14_VARIABLE_PHASE || C_CLKOUT13_VARIABLE_PHASE || C_CLKOUT12_VARIABLE_PHASE || C_CLKOUT11_VARIABLE_PHASE || C_CLKOUT10_VARIABLE_PHASE || C_CLKOUT9_VARIABLE_PHASE || C_CLKOUT8_VARIABLE_PHASE || C_CLKOUT7_VARIABLE_PHASE || C_CLKOUT6_VARIABLE_PHASE || C_CLKOUT5_VARIABLE_PHASE || C_CLKOUT4_VARIABLE_PHASE || C_CLKOUT3_VARIABLE_PHASE || C_CLKOUT2_VARIABLE_PHASE || C_CL KOUT1_VARIABLE_PHASE || C_CLKOUT0_VARIABLE_PHASE)" evaluates to FALSE. Please remove the port from your design - D:\HDMI_RX_SYSACE\microblaze\microblaze.mhs line 136 ERROR:EDK:4070 - INSTANCE: clock_generator_0, PORT: PSEN - invalid port in use when ISVALID="(C_CLKOUT15_VARIABLE_PHASE || C_CLKOUT14_VARIABLE_PHASE || C_CLKOUT13_VARIABLE_PHASE || C_CLKOUT12_VARIABLE_PHASE || C_CLKOUT11_VARIABLE_PHASE || C_CLKOUT10_VARIABLE_PHASE || C_CLKOUT9_VARIABLE_PHASE || C_CLKOUT8_VARIABLE_PHASE || C_CLKOUT7_VARIABLE_PHASE || C_CLKOUT6_VARIABLE_PHASE || C_CLKOUT5_VARIABLE_PHASE || C_CLKOUT4_VARIABLE_PHASE || C_CLKOUT3_VARIABLE_PHASE || C_CLKOUT2_VARIABLE_PHASE || C_CLK OUT1_VARIABLE_PHASE || C_CLKOUT0_VARIABLE_PHASE)" evaluates to FALSE. Please remove the port from your design - D:\HDMI_RX_SYSACE\microblaze\microblaze.mhs line 136 ERROR:EDK:4070 - INSTANCE: clock_generator_0, PORT: PSINCDEC - invalid port in use when ISVALID="(C_CLKOUT15_VARIABLE_PHASE || C_CLKOUT14_VARIABLE_PHASE || C_CLKOUT13_VARIABLE_PHASE || C_CLKOUT12_VARIABLE_PHASE || C_CLKOUT11_VARIABLE_PHASE || C_CLKOUT10_VARIABLE_PHASE || C_CLKOUT9_VARIABLE_PHASE || C_CLKOUT8_VARIABLE_PHASE || C_CLKOUT7_VARIABLE_PHASE || C_CLKOUT6_VARIABLE_PHASE || C_CLKOUT5_VARIABLE_PHASE || C_CLKOUT4_VARIABLE_PHASE || C_CLKOUT3_VARIABLE_PHASE || C_CLKOUT2_VARIABLE_PHASE || C _CLKOUT1_VARIABLE_PHASE || C_CLKOUT0_VARIABLE_PHASE)" evaluates to FALSE. Please remove the port from your design - D:\HDMI_RX_SYSACE\microblaze\microblaze.mhs line 136 ERROR:EDK:4070 - INSTANCE: clock_generator_0, PORT: PSDONE - invalid port in use when ISVALID="(C_CLKOUT15_VARIABLE_PHASE || C_CLKOUT14_VARIABLE_PHASE || C_CLKOUT13_VARIABLE_PHASE || C_CLKOUT12_VARIABLE_PHASE || C_CLKOUT11_VARIABLE_PHASE || C_CLKOUT10_VARIABLE_PHASE || C_CLKOUT9_VARIABLE_PHASE || C_CLKOUT8_VARIABLE_PHASE || C_CLKOUT7_VARIABLE_PHASE || C_CLKOUT6_VARIABLE_PHASE || C_CLKOUT5_VARIABLE_PHASE || C_CLKOUT4_VARIABLE_PHASE || C_CLKOUT3_VARIABLE_PHASE || C_CLKOUT2_VARIABLE_PHASE || C_C LKOUT1_VARIABLE_PHASE || C_CLKOUT0_VARIABLE_PHASE)" evaluates to FALSE. Please remove the port from your design - D:\HDMI_RX_SYSACE\microblaze\microblaze.mhs line 136

後來去對照原本ml605的clock generator跟後來的少了兩個clock還有PSCLK,PSEN,PSINCDEC,PSDONE

所以把clock generator的值改成跟ml605一樣,require group為mmcm0,記得在最後一個clock的variable phase改成true,這樣才會enable PSCLK,PSEN,PSINCDEC,PSDONE這四個pin

把port也都接上

這樣就可以順利generate netlist了!

比較奇怪的是,這邊的型號是xc6vcx75t,但是如果選高階的型號,clock generator會自動產生好,不用自己再調,所謂一分錢一分貨嗎 -.- 

------------------------------------ 以上根本就是因為腦殘-------------------------------------

後來因為DDR的頻率跟ml605設的不一樣,而且沒有辦法改

原來是因為每個系列有不同的DDR Frequency

發現我根本FPGA選錯了,我要用的是xc6vlx75t,400 Mhz,然後-1 speed

建立完microblaze以後發現很神奇的clock generator都不用自己調了

已經幫你建好跟ml605一樣的

在ml605上有點我不太明白

因為在板子上的DDR3是MT4JSSF6464XX,WIDTH為64bits

但是在ml605上的micorblaze卻是預設MT41J64M16XX,WIDTH為8 bits

但是在測試CF上沒有問題,可能我只是用DDR3來heap,steak,不是大量的讀寫?????

我在xc6vlx75t上先測試使用MT4JSSF6464XX,DDR3的Bank selection就先照預設

在UG406中P.55頁有提到UCF得設定規則,還有其它的timing constraint 需要設定

BUFIO與BUFR

     1. 與DQS相關的pin必須放在同一個bank

2. data與address必須要放在鄰近的區域
3. system clock必須放在GC ,banks (24, 25, 34, and 35)
4. dqs與ck必須放在differential pin

These rules are verified from the input UCF: • If a pin is allocated to more than one signal, the tool reports an error. • Further verification does not occur if the UCF does not adhere to the uniqueness property. • The pins related to one DQS set should be allocated in the same bank. • When the frequency of the configuration is more than 400 MHz, the IOB distance calculation is verified. • The maximum distance of the DQ/DM and DQS should not be more than eight IOB pads. Violation of this rule generates a warning. • The span of the DQS set should not be greater than 13 IOB pads. Violation of this rule is treated as a warning. • If the DQS set is allocated at the center of the bank, the IOB pad distance is calculated with respect to the clock tree instead of the DQS pair. The distance between the set pin and clock tree should be no more than 13 IOBs. • Banks should be allocated for the address and data within the vicinity arena. • An error occurs if a bank is allocated outside the vicinity arena. • The system clock bank can be selected adjacent to the GC bank (24, 25, 34, and 35) or to the bank adjacent to the capture clock bank. • The system clock bank can be selected adjacent to the capture clock bank only when the frequency of this controller is not repeated in any of the other controllers. If the frequency of this controller is repeated in any of the other controllers, the system clock group must be allocated to any of the GC banks (24, 25, 34, and 35) but not to the bank where only CC pins are available (this occurs when a bank adjacent to the capture clock bank is used). • The signal pairs sys_clk and clk_ref are allocated to the CC pair or GC pair pins (for a bank adjacent to the capture clock bank) or to the GC pair pins (for GC banks). • The memory clock signals (CK and CK#) should be allocated to the differential pair pins (P-N pair). • The DQS pair should be allocated to the differential pair pins. • The capture clock (BUFIO) and resynchronization clock (BUFR) constraints are verified as follows: • The capture clock LOC constraint should be associated with its corresponding strobe set. Otherwise, the tool reports an error and provides the valid pins to correct the constraints and rerun the verification. • The resynchronization clock LOC constraint should be associated with the corresponding column where its related strobes are allocated. If the resynchronization clock is not associated with its corresponding strobe pins, the tool reports an error and provides the valid pins to correct the constraints and rerun the verification. • In the DCI CASCADE syntax, the selected configuration should require the master bank. • The slave banks provided should be valid. • A valid mixed-mode clock manager (MMCM) constraint value should be provided, otherwise a warning is generated. If the UCF satisfies the above rules, the updated design is generated. The design: • Provides the latest HDL. • Updates the UCF with the latest clock constraints or any timing ignores (TIGs) provided by keeping the same pinout. • Generates even the compatible UCFs if the project loaded contains the compatible FPGA selection.

在ddr3設定的另一頁有更詳細的解說,不過應該按照預設下去定pinout就會都遵守規則

The FPGA bank diagram of the Bank selection page is an architectural view of physical representation of the selected part. By default MIG will use the recommended selection. Possible Address/Control banks and Data banks are restricted according to the Virtex-6 rules for different frequencies. Choose the banks you would like to use for your memory interface. You do not get to select the actual pins. By default MIG will use any available pins for the memory interface in the selected banks. Design Rules: Design maximum frequency: -1 FPGA speed grade devices: 400 MHz -2 and -3 FPGA speed grade devices: 533 MHz Only -2 FPGA speed grade CXT device is supported with only 303 MHz frequency support Low power Virtex-6 devices are supported with only 303 MHz frequency support For frequencies above 333 MHz, only the data widths up to 72 bits are allowed. For frequencies of 333 MHz and below, data widths up to 144 bits are allowed Memory type, Memory parts and Data Widths are restricted based on the selected FPGA device, FPGA device speed grade and the design frequency Bank Selection Rules : Address/Control groups can be selected only in the inner column banks First bank selected for Address/Control group will have CK[0] and CK#[0] pins Bank consisting of CK[0] and CK#[0], will have MMCM utilized in that H-Row For design frequencies above 400 MHz and higher, only Inner Column banks are allowed for Data group selection. For design frequencies of 400 MHz and below, both Inner and Outer Column banks are allowed for Data group selection Either Inner or Outer Column banks are only allowed for selection Inner and Outer column banks which reside one row above, one row below and on the same row of bank consisting of CK[0] and CK#[0] will be enabled for Data group pin selections This restrictions is represented by a boundary box called vicinity box System Clock group can be selected only in the banks consisting of GC pins or in the inner column banks which are in the same H-ROW of allocated MMCM Design control and status pins viz., sys_rst, error,.. etc., are allocated in System Clock bank System Clock group and rest of the design group pins (Address/Control group and Data groups) cannot co-exist in a same bank due to different voltage standards A Master bank must be selected for each column if asked for System Clock group bank cannot be selected as Master bank Pin Allocation Rules : Address/Control group: Consists of A, BA, CK, CK#, CKE, CS#, RAS#, CAS#, WE#, ODT, RESET# memory signals Only inner column banks are allowed for selection Memory clock signals (CK[0] and CK#[0]) will be allocated to differential pair pins (P-N pair) VRN/VRP pins will be utilized for pin allocation. In this case, DCI Cascading will be applied in order to support DCI Standard on Address/Control group signals VREF pins are utilized for pin allocation if Data group is not allocated in Address/Control group bank Data group: Consists of DQ, DM, DQS and DQS# memory signals DQS group consists of DQ and DM pins associated with its corresponding DQS and DQS# pins DQS and DQS# pins will be allocated to P-N pair Each DQS group in a bank is associated with a CC-P pin reserved for BUFIO In a column of banks allocated with Data group pins, at least one bank will have a CC-P pin reserved for BUFR VREF pins are not utilized for pin allocation If VRN/VRP pins are utilized for pin allocation in a bank then to support DCI, DCI Cascading feature is applied. In this case, a Master bank has to be selected System Clock group: Consists of Design Clocks: sys_clk_p, sys_clk_n (DIFFERENTIAL) or sys_clk (SINGLE-ENDED) Reference Clocks: clk_ref_p, clk_ref_n (DIFFERENTIAL) or clk_ref (SINGLE-ENDED) 'sys_rst', design reset pin 'error' and 'phy_init_done' status pins For DIMM designs, this group consists of sda and scl pins For ECC enabled designs, this group consists of ECC error pin 'app_ecc_multiple_err' 'error' pin is allocated only for example designs Only Inner Column banks are allowed for selection GC pins are allocated for Design Clocks and Reference Clocks, if the System Clock bank is any one of Banks 35 or 34 or 25 or 24 CC pins are allocated for Design Clocks and Reference Clocks, if the System Clock bank is in the Address/Control bank H-Row of allocated MMCM (even if the bank is any one of banks 35 or 34 or 25 or 24) This group is associated with 2.5v IO Standard Master bank: Except System Clock bank, any bank in a given column of banks which are only within the vicinity can be selected as Master bank A Master bank will always have VRN/VRP pins unused. Due to this in a given bank VRN/VRP pins will be reserved if it is selected as Master bank All the Data group banks in the given column acts as Slave banks if a Master bank is selected in that column. The same is given in the generated UCF file BUFR Allocation Rules: In a column of banks, if there are Data groups pins allocated, then at least one bank must have CC-P pin reserved for BUFR In a column of banks, if there is only one bank allocated with Data group pins, then the same bank will have a CC-P pin reserved for BUFR The above rule is valid for x8 and x16 part designs For x4 part designs, in order to accommodate more data width in a single bank, BUFR is always allocated in the bank below or above the selected Data group bank In a column of banks, if there are two consecutive banks allocated with Data group pins, then the Data group bank (of Address/Control bank row) will have a CC-P pin reserved for BUFR In a column of banks, if there are three consecutive banks allocated with Data group pins, then the middle bank allocated for Data group pins will have a CC-P pin reserved for BUFR In a column of banks, if there are two banks allocated with Data group pins and when the intervening bank (Address/Control bank row) is left idle, then a CC-P pin is reserved in the same idle bank If the Data group vicinity is only two rows of banks, then in a column of banks if one bank is allocated with Data group pins and the other bank is allocated with Non-Data group pins (Address/Control group or System Clock group), the Non-Data group bank will have a CC-P pin reserved for BUFR If the Data group vicinity is three rows of banks, then in a column of banks if at least one bank is allocated with Data group pins and the middle bank (Address/Control bank row) is allocated with Non-Data group pins (Address/Control group or System Clock group), the Non-Data group bank will have a CC-P pin reserved for BUFR For any group, priority order for pin allocation in banks is followed In a given column of banks, preference of pin allocation in banks is in descending order. A top-down order of banks is followed In a given bank, pins are allocated in top-down order Priority order of columns: Inner Left Column, Inner Right Column, Outer Left Column, Outer Right Column Notes: It is not possible to fit an eight bit design with an eight bit part in single bank without using internal VREF option. Address/Control group requires 26 pins One additional pin is reserved for BUFR in Address/Control bank. See above BUFR Allocation Rules The Available IOs(AIOs) will be 13 ( 40-27) On selecting Data in Address/Control Bank, Available IO(AIO) count will change to 11, Since 8-bit data requires total of 12 pins, it is not possible to use Address/Control bank for Data group allocation

第一次先選new design

完成以後再重新打開一次選fixed pin out,可以直接儲存pin location貼到ucf中

之後BUFIO與BUFR也可以如法炮製

在BUFIO與BUFR的constraint中,有個小地方要改成不指定的路徑

INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" LOC = "OLOGIC_X2Y23";

在UG406 的P.109 – P.112中有提到Core Constraint

其中location constraint (OSERDES, IODELAY)上面已經有了

而timing constraint才是頭大的地方阿!!!!!

這個constraint是BUFR用來同步iserdes收到的資料輸入CLB logic中, 必須是memory clock的兩倍現在我設定的memory clock 是400 MHz 所以是 2.5 ns x2 為 5ns, 本來我是用5ns下去繞,但是timing的slack是負的,後來看到plb裡面預設的constraint寫說這應該會太緊,使用者可以設成mmcm0,也就是10 ns,後來得到正的slack

這個應該是用來保持DQ,DQS的rising,falling edge

NET "clk_p" TNM_NET = TNM_sys_clk; TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 5 ns; # Constrain BUFR clocks used to synchronize data from IOB to fabric logic # Note that ISE cannot infer this from other PERIOD constraints because # of the use of OSERDES blocks in the BUFR clock generation path NET "*/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync[?]" TNM_NET = TNM_clk_rsync; TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 10 ns; # This is over-constraint for 200MHz, user can relax it to match mpmc_clk0 # Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling # edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for # that particular flop. Mark this path as being a full-cycle, rather than # a half cycle path for timing purposes. NOTE: This constraint forces full- # cycle timing to be applied globally for all rising->falling edge paths # in all resynchronizaton clock domains. If the user had modified the logic # in the resync clock domain such that other rising->falling edge paths # exist, then constraint below should be modified to utilize pattern # matching to specific affect only the DQ/DQS ISERDES.Q outputs TIMEGRP "TG_clk_rsync_rise" = RISING "TNM_clk_rsync"; TIMEGRP "TG_clk_rsync_fall" = FALLING "TNM_clk_rsync"; TIMESPEC "TS_clk_rsync_rise_to_fall" = FROM "TG_clk_rsync_rise" TO "TG_clk_rsync_fall" "TS_sys_clk" * 2; # This is over-constraint for 200MHz, user can relax it to match mpmc_clk0 # Signal to select between controller and physical layer signals. Four divided by two clock # cycles (4 memory clock cycles) are provided by design for the signal to settle down. # Used only by the phy modules. INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL"; TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = "TS_sys_clk"*4; # This is over-constraint, user can relax it to match 4 memory clock cycles

location constraint (OSERDES, IODELAY) 雖然可以自己產生,但是也要注意一下規則

CONFIG_PROHIBIT 用來避免其它邏輯使用相同的PIN

Resynchronization Clock Forwarding and Distribution Elements(BUFR)

一定要接在MRCC或是SRCC的P side

DQ如果無法全接在同一個Bank也要接緊臨上下的

Capture Clock Forwarding and Distribution Elements ( BUFIO)

一定要接在MRCC或是SRCC的P side

DQ,DQS,DM 一定要放在相同的Bank

ml605範例

################################################################################################## ##The following locations must be reserved and cannot be used for external I/O because ## ##the I/O elements associated with these sites (IODELAY, OSERDES, and associated routing) ## ##are used to generate and route the clocks necessary for read data capture and synchronization ## ##to the core clock domain. These pins should not be routed out on the user's PCB ## ################################################################################################## ################################################################################################## ##The logic of this pin is used internally to drive a BUFR in the column. This chosen pin must ## ##be a clock pin capable of spanning to all of the banks containing data bytes in the particular## ##column. That is, all byte groups must be within +/- 1 bank of this pin. This pin cannot be ## ##used for other functions and should not be connected externally. If a different pin is chosen,## ##he corresponding LOC constraint must also be changed. ## ################################################################################################## ############################################################################################### ## Note: ML605 optional to comment out these lines. If design has more I/O than just MIG 3.3 ## example design, leave CONFIG PROHIBIT definitions in design to permit reservation of ## these I/O pins for MIG use. ############################################################################################### ## CONFIG PROHIBIT = F19,G18; ###################################################################################### ## Place RSYNC OSERDES and IODELAY: (locations for ML605) ## ###################################################################################### # CLK_RSYNC[0]: Site M12 INST "*/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" LOC = "OLOGIC_X2Y139"; INST "*/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" LOC = "IODELAY_X2Y139"; INST "*/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" LOC = "BUFR_X2Y6"; # CLK_RSYNC[1]: Site C29 INST "*/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync" LOC = "OLOGIC_X1Y139"; INST "*/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync" LOC = "IODELAY_X1Y139"; INST "*/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" LOC = "BUFR_X1Y6"; ################################################################################################## ##The logic of this pin is used internally to drive a BUFIO for the byte group. Any clock ## ##capable pin in the same bank as the data byte group (DQS, DQ, DM if used) can be used for ## ##this pin. This pin cannot be used for other functions and should not be connected externally. ## ##If a different pin is chosen, the corresponding LOC constraint must also be changed. ## ################################################################################################## ## CONFIG PROHIBIT = B20,C28,C29,F21,F25,H19,L13,M12; ###################################################################################### ##Place CPT OSERDES and IODELAY: ## ###################################################################################### # DQS[0]: Site C13 INST "*/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt" LOC = "OLOGIC_X2Y137"; INST "*/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt" LOC = "IODELAY_X2Y137"; # DQS[1]: Site L13 INST "*/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt" LOC = "OLOGIC_X2Y141"; INST "*/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt" LOC = "IODELAY_X2Y141"; # DQS[2]: Site K14 INST "*/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt" LOC = "OLOGIC_X2Y143"; INST "*/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt" LOC = "IODELAY_X2Y143"; # DQS[3]: Site F21 INST "*/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt" LOC = "OLOGIC_X1Y179"; INST "*/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt" LOC = "IODELAY_X1Y179"; # DQS[4]: Site B20 INST "*/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt" LOC = "OLOGIC_X1Y181"; INST "*/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt" LOC = "IODELAY_X1Y181"; # DQS[5]: Site F25 INST "*/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt" LOC = "OLOGIC_X1Y137"; INST "*/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt" LOC = "IODELAY_X1Y137"; # DQS[6]: Site C28 INST "*/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt" LOC = "OLOGIC_X1Y141"; INST "*/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt" LOC = "IODELAY_X1Y141"; # DQS[7]: Site D24 INST "*/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt" LOC = "OLOGIC_X1Y143"; INST "*/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt" LOC = "IODELAY_X1Y143";

在範例裡面學到原來ucf也可以這樣寫阿

這樣就不用在每個pin後面定義iostandard了! 現在才知道有這招!!!!

################################################################################ # I/O STANDARDS ################################################################################ NET "ddr3_dq[*]" IOSTANDARD = SSTL15_T_DCI; NET "ddr3_addr[*]" IOSTANDARD = SSTL15; NET "ddr3_ba[*]" IOSTANDARD = SSTL15; NET "ddr3_ras_n" IOSTANDARD = SSTL15; NET "ddr3_cas_n" IOSTANDARD = SSTL15; NET "ddr3_we_n" IOSTANDARD = SSTL15; NET "ddr3_reset_n" IOSTANDARD = SSTL15; NET "ddr3_cs_n[*]" IOSTANDARD = SSTL15; NET "ddr3_odt[*]" IOSTANDARD = SSTL15; NET "ddr3_cke[*]" IOSTANDARD = SSTL15; NET "ddr3_dm[*]" IOSTANDARD = SSTL15; ## ML605 200 MHz LVDS oscillator - single input clock design (2.5V bank) NET "sys_clk_p" IOSTANDARD = LVDS_25; NET "sys_clk_n" IOSTANDARD = LVDS_25; ## ML605 CPU_RESET switch (1.5V bank) NET "sys_rst" IOSTANDARD = SSTL15; NET "ddr3_dqs_p[*]" IOSTANDARD = DIFF_SSTL15_T_DCI; NET "ddr3_dqs_n[*]" IOSTANDARD = DIFF_SSTL15_T_DCI; NET "ddr3_ck_p[*]" IOSTANDARD = DIFF_SSTL15_T_DCI; NET "ddr3_ck_n[*]" IOSTANDARD = DIFF_SSTL15_T_DCI;

後記,64 bits的DDR我怎麼都繞不進去,Timing constraint改了又改還是negativ slack

後來決定還是用8 bits好了,至少slack不會是負的阿!!!

果然下constraint能力還是太弱了!!!!