Ref
: Synchronous Resets? Asynchronous
Resets? I am so confused! How will I ever know which to use? -
Clifford E. Cummings
延伸閱讀
! Asynchronous
& Synchronous Reset
Design
Techniques - Part Deux
-Clifford E. Cummings
這篇文章是我讀得這篇的第二版,有多加一些東西,但是也把後面的multi
ASIC reset拿掉,沒有時間看完,有空可以再看一次!
Synchronous
Reset
與clk同步的reset
directive //
synopsys sync_set_reset "rst_n"
the
sync_set_reset
directive
does not affect the logical behavior of a design,
instead it only impacts the functional implementation of a design. A
wise engineer would prefer to avoid re-synthesizing the design late
in the project schedule and would add the sync_set_reset
directive to all RTL
code from the start of the project.
優點
:
沒有不穩定(metastability)
的問題,其保證整個電路都是同步
在有些設計裡面需要自己產生reset訊號,這時候適合用synchronous
reset
缺點
:
1.
與非同步比需要比較多的邏輯,但是現在科技日新月異,die可以塞非常多邏輯,所以差別
不太大
2. 需要一直提供Clock,
雖然這clock可以當作filter來消除reset
glitches, 但是如果這些
glitches發生在active
clock edge,也會造成FF進入metastable,
速度較慢,且需要保證reset拉得夠長到active
clock edge
在模擬的時候,reset可能會被設成X's,有些模擬器不支援這種情況,
所以可能會block
out synchronous reset.
因為synchronous
reset需要一個clk,在某些電路上可能會造成困擾,譬如在設計中有tristate
bus,在這種電路中需要power
on asynchronous reset
注意reset不在sensitivity
list裡面
下面的例子是reset
為active
high,如果reset
active low,就要改為if
( reset = '0' )
Asynchronous
Reset
與clk不同步的reset
The
approach to synthesizing asynchronous resets will depend on the
designers approach to the reset buffer tree. If the reset is driven
directly from an external pin, then usually doing a set_drive
0 on the reset pin and doing a set_dont_touch_network
on the reset net will protect the net from being modified
by synthesis. However, there is at least one ESNUG article that
indicates this is not always the case[16].
One
ESNUG contributor[15] indicates that sometimes set_resistance
0 on the reset net might also be needed. And our
colleague, Steve Golson, has pointed out that you can set_resistance
0 on the net, or create a custom wireload model with
resistance=0 and apply it to the reset input port with the command:
set_wire_load
-port_list reset A
recently updated SolvNet article also notes that starting with
Synopsys release 2001.08 the definition of ideal nets has slightly
changed[24] and that a set_ideal_net command
can be used to create ideal nets and “get no timing
updates,
get no delay optimization, and get no DRC fixing.”
Another
colleague, Chris Kiegle, reported that doing a set_disable_timing on
a net for pre-v2001.08 designs helped to clean up timing reports[2],
which seems to be supported by two other SolvNet articles, one
related to synthesis and another related to Physical Synthesis, that
recommend usage of both a set_false_path
and a
set_disable_timing
command[21][25].
優點
: 與同步比需要比較少的邏輯,不需要一直提供Clock,速度較快
The
biggest advantage to using asynchronous resets is that, as long as
the vendor library has
asynchronously
resetable flip-flops, the data path is guaranteed to be clean.
缺點
: 最大的問題在於deassertion的時候,如果在active
clock edge附近的話,有不穩定(metastability)
的問題,ASIC可能會失去reset
state,另外跟同步相同的問題,會有因為glitch或是雜訊造成的偽reset(spurious
reset)使系統進入metastable.
注意reset在sensitivity
list裡面
下面的例子是reset
active high,如果reset
active low,就要改為if
( reset = '0' )
Clifford
E. Cummings 的paper中有建議的coding
style
Synchronous
reset flip-flops with non reset follower flip-flops
上面的第一種形式比較常被應用,第二種只是展示功能
Modeling
Verilog flip-flops with asynchronous reset and asynchronous set
For
those rare designs where reset and set are both permitted to be
asserted simultaneously and then reset is removed
first,
the fix to this simulation problem is to model the flip-flop using
self-correcting code enclosed within the
translate_off/translate_on
directives and force the output to the correct value for this one
condition. The best
recommendation
here is to avoid, as much as possible, the condition that requires a
flip-flop that uses both
asynchronous
set and asynchronous reset. The code in Example 6 shows the fix that
will simulate correctly and
guarantee
a match between pre- and post-synthesis simulations. This code uses
the translate_off/translate_on
directives
to force the correct output for the exception condition[4].
只有asynchronous
會有reset,set的情況,
reset與set同時assert,
reset 先remove.
下面的例子是使用非同步,但是設計者不放reset在data
path裡面(不太明白耶!!!)
Reset
Synchronizer
結論!
每一個使用asynchronous
reset的ASIC
design一定要有一個Reset
Synchronizer !
Reset
Synchronizer具有同步與非同步的優點,先用非同步進來,用一個reg擋住,再用同步傳出去,下面的例子reset為active
low
Reset
distribution tree
reset distribution tree的負載跟clock
distribution tree 一樣重
Unlike
clock signals, skew between reset signals is not critical as long as
the delay associated with any reset signal is short enough to allow
propagation to all reset loads within a clock period and still meet
recovery time of all destination registers and flip-flops
The
safest way to clock a reset
tree (synchronous or asynchronous reset) is to clock the
internal-master-reset flip-flop from a leaf-clock of the clock tree
as shown in Figure
9. If this approach will meet timing, life is good. In most cases,
there is not enough time to have a clock pulse traverse the clock
tree, clock the reset-driving flip-flop and then have the reset
traverse the reset tree, all within one clock period.
Reset-glitch
filtering
Cliff介紹一個消除reset
glitch的方法,
利用delay來消除glitch,reset
input必須要是schmitt
trigger.
In
order to add the delay, some vendors provide a delay hard macro that
can be hand instantiated. If such a delay macro
is not available, the designer could manually instantiate the delay
into the synthesized design after optimization – remember
not to optimize this block after the delay has been inserted or it
will be removed. Of
course the elements could have don’t touch attributes applied to
prevent them from being removed. A second approach is to instantiated
a slow buffer in a module and then instantiated that module multiple
times to get the desired delay.
Multi-clock
reset issues
之前討論reset在deassertion的時候可能會造成metastable,cliff舉出下列兩種方法來解決
non-coordinated
reset
removal,reset只要在相近的時間點移除,不管是不是在一個clk之內
sequenced
coordination of reset removal.
要確定第一級reset移掉之後,要確定logic已經activate在另兩級移掉reset之前
文章後面都在介紹multi
ASIC的reset,這部分如果以後工作需要的話再看吧!
