Xilinx Vivado packaging IP 筆記

Reference

Vivado Design Suite Tutorial

Creating and Packaging Custom IP(UG1119)

除了IP本身的constraint以外,還需要另外準備一個out-of-context(OOC) constraint給parent design來定義external clocking. 如果IP內的clock為local或是經由IBUF,則寫在IP本身的constraint中, 如果clock是由parent design 提供,則須寫在OOC constraint中.這樣如果IP被別的設計引用,則會自動繼承parent design clock.

IMPORTANT: A synthesized design checkpoint (DCP) is created as part of the default Out-of-Context (OOC) design flow for IP packaging and use.

For more information on the Out-Of-Context (OOC) design flow, and the use of the DCP file, see the Vivado Design Suite User Guide: Designing with IP (UG896).

IP的constraint 會比top level先讀入,可以經由processing oder 來修改,但是如果在ip constraint中有set_max_delay則需要將processing oder 設為late

TIP: Xilinx delivered IP with “_clock” appended to the XDC filename are all marked for LATE processing.

寫完ooc constraint以後還要將屬性的used in 加入out_of_context(p.13)

IMPORTANT: The USED_IN property for an OOC XDC file should be {synthesis implementation out_of_context}. If it is just out_of_context, it is not used during synthesis or implementation.