Reference:
Design
Compiler® User Guide Version
C-2009.06, June 2009
clock
gating
The control of a clock
signal by logic (other than inverters or buffers), either to shut
down the clock signal at
selected times or to modify the clock pulse characteristics.
clock
latency
The amount of time that a
clock signal takes to be propagated from the clock source to
a specific point in the
design. Clock latency is the sum of source latency and network
latency.
Source latency is the
propagation time from the actual clock origin to the clock
definition point in the
design. Network latency is the propagation time from the clock
definition point in the
design to the clock pin of the first register.
You use the
set_clock_latency command to specify clock latency
clock
skew/clock uncertainty
The maximum difference
between the arrival of clock signals at registers in one clock
domain or between clock
domains. Clock skew is also known as clock uncertainty. You
use the
set_clock_uncertainty command to specify the skew characteristics of
one or more clock networks.
critical
path
The path through a circuit
with the longest delay. The speed of a circuit depends on the
slowest register-to-register
delay. The clock period cannot be shorter than this delay or
the signal will not reach
the next register in time to be clocked.
The
most critical path is not necessarily the longest combinational path
in a sequential design,
because
paths can be relative to different clocks at path startpoints and
endpoints.
design
constraints
The designer’s
specification of design performance goals, that is, the timing and
environmental restrictions
under which synthesis is to be performed. Design Compiler
uses these constraints—for
example, low power, small area, high-speed, or minimal
cost—to direct the
optimization of a design to meet area and timing goals.
There are two categories of
design constraints: design rule constraints and design
optimization constraints.
• Design rule constraints
are supplied in the technology library. For proper functioning
of the fabricated circuit,
they must not be violated.
• Design optimization
constraints define timing and area optimization goals.
Design Compiler optimizes
the synthesis of the design in accordance with both sets of
constraints; however, design
rule constraints have higher priority.
false
path
A path that you do not want
Design Compiler to consider during timing analysis. An
example of such a path is
one between two multiplexed blocks that are never enabled
at the same time, that is, a
path that cannot propagate a signal.
You use the set_false_path
command to disable timing-based synthesis on a
path-by-path basis. The
command removes timing constraints on the specified path.
hold
time
The time that a signal on
the data pin must remain stable after the active edge of the
clock. The hold time creates
a minimum delay requirement for paths leading to the
data pin of the cell.
You calculate the hold time
by using the formula
hold = max clock delay - min
data delay
setup
time
The time that a signal on
the data pin must remain stable before the active edge of the
clock. The setup time
creates a maximum delay requirement for paths leading to the
data pin of a cell.
You calculate the setup time
by using the formula
setup = max data delay - min
clock delay
slack
A value that represents the
difference between the actual arrival time and the required
arrival time of data at the
path endpoint in a mapped design. Slack values can be
positive, negative, or zero.
A positive slack value
represents the amount by which the delay of a path can be
increased without violating
any timing constraints. A negative slack value represents
the amount by which the
delay of a path must be reduced to meet its timing
constraints.
Retiming是藉由移動電路中Registers位置以達改善電路效能的合成方法。其不會改變電路的Register
stage及功能，但會影響Registers的數目。
Process
of optimally distributing registers throughout a circuitminimize
the clock periodminimize
the number of registers
Incremental
compile supports adaptive retiming, that is, compile_ultra
-inc -retime.
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